PLL Compiler verification is a contentious issue. In fact the very concept of compiler technology is contentious as it beings into play the trade off between flexibility and reliability. On one hand the flexibility of being able to optimize the design to your precise frequency requirements, centering performance just where you need it versus the reliability that one gets by using a fixed silicon proven solution. Indeed you cannot ignore the risks posed by using a compiler-generated design that hasn't been implemented exactly in silicon. You can however, control and manage those risks by using a compiler that has been through a careful silicon qualification program.

CEVA absolutely believes in the principle of verifying IP in silicon. The challenge is how to verify the entire design space of a compiler using fixed PLL instantiations. The answer is you cannot. Fixed instantiations only tell you about fixed points in the design space and this alone is not sufficient to verify a compiler. CEVA has developed a unique approach implemented on 2 generations of 130nm and our new 90nm technology, which uses a configurable calibration chip for verification of the PLL Compiler. This calibration chip serves as a verification device but also serves as a highly valuable demonstration for customers who may be concerned about PLL integrity.

The calibration chip includes:

One configurable PLL. The configurable PLL can be set to replicate virtually any PLL capable of being designed by the Compiler thus providing real silicon evidence of the performance that is likely to be achieved by your design.

A number of fixed PLL instantiations. The fixed PLLs, which are generated by the PLLXpert Compiler, are used to calibrate the configurable PLL. These demonstrate that the performance of the configurable device matches that of the fixed devices executed by the compiler. Thus the configurable PLL can be used to truly verify the design space of the compiler.

A structure which enables the measurement of Static Phase Offset in the PLL. This parameter is critical to PLLs used in Deskew applications.

A structure incorporating a large digital block enabling a measurement of the sensitivity of the PLL to adjacent on-chip noise sources.

A facility to evaluate the sensitivity of the PLL to Vdd noise.

Hardware calibration is further supported by simulation using an automated software test system which:

Exercises the PLLXpert design software to generate a large sample of the set of analog loop possibilities.

Netlists all possible Charge Pump, VCO, and feedback divider possibilities and automatically checks performance parameters through simulation. In addition a very large sample of Loop Filter Possibilities are netlisted and simulated.

Automatically generates all GDSII possibilities and analyses each output using DRC and LVS routines.