CEVA's ring oscillator based PLL architecture has been targeted specifically for ASIC and SoC embedded applications and has been proven over six process generations by CEVA and our customers. Starting initially on 0.5µm technologies the PLL architecture has been scaled and developed through six generations of technologies down to the latest 130nm and 90nm geometries. The technology barrier of operating at 1 Volt Vdd has been overcome by CEVA using proprietary design techniques.

Our new generation of 130nm and 90nm products utilize these techniques unlocking the major power saving advantages of lower voltage and geometry sizes, whilst at the same time maintaining excellent jitter performance. The PLL architecture is both flexible and scalable to match the design constraints of a particular application.

CEVA's PLLs are designed for optimum jitter performance whilst at the same time maintaining fast lock time and low power consumption.

Details of the performance of CEVA's PLLs can be found in the datasheets available from our Downloads page.