PLL Architecture

PLLXpert, an automated PLL compiler technology has transformed analog PLL design and delivery though enabling digital and analog designers to rapidly design robust clock synthesizers on a range of standard CMOS processes. Through PLLXpert's online interface to the PLLXpert compiler, a designer can either download from a broad portfolio of silicon proven PLLs or create a custom PLL. PLLXpert delivers a complete design kit including datasheets, verilog models, and the necessary files for logic synthesis and place and route. These deliverables enable the designer to fully validate the integration of the PLL into the IC by optimising the PLL until it meets evolving system requirements including GDSII immediate delivery on final demand. No prior training, no in-depth PLL design knowledge or additional EDA tools are required.

PLLXpert Online leverages years of PLL design and development at CEVA. Recognizing both the critical importance of PLLs, and CEVA's unique compiler technology, the company established the PLLXpert Business Unit in 2001 and since has established a worldwide base of licensing customers.

PLLXpert Compiler

PLLXpert is a PLL compiler capable of designing a range of PLL IP cores configurable to specific user requirements. The compiler covers multiple foundry/customer processes currently spanning 0.25um, 0.18um, 0.13um and the latest 90nm processes. Roadmap R&D is targeting 65nm processes.

The PLLs generated are based on a silicon proven architecture tried and tested in various calibration chips over six process generations. The result is always a right-first-time clock synthesizer, optimized for area, power and jitter performance, in the shortest possible design time and minimal design effort. The clock outputs of PLLXpert achieve jitter between 4ps rms and 10ps rms leading to very stable clocks in the digital design.

The PLLXpert compiler conducts auto-layout and delivers datasheets, verilog model, CDL Netlist and a GDSII file. Not only does PLLXpert dramatically reduce design time cycles, it also removes risk from the PLL design process through both the compilers extensive validation and silicon pre-verification of each process

PLL Compiler Silicon Qualification

PLLXpert enables to the designer to rapidly develop silicon proven PLL cores on multiple silicon processes. To ensure risk-free PLLs, each silicon process has been verified by a companion PLL compiler calibration chip which validates the extremes of the design range.

PLL compiler silicon qualification includes;

0.18um Designs

• Verified in silicon using 3 specific PLL instantiations designed to test the extremes of the PLLXpert design space. Evaluation reports available on the web.

  0.13um and 90nm Designs

• A configurable calibration chip containing multiple, selectable VCOs, configurable loop filters and programmable dividers.

• Number of fixed PLL instantiations for comparison

• A software application is used to configure the test chip for the desired performance.

• Evaluation reports available

PLLXpert Process Online Availability

The designer can either leverage the portfolio of high-performance, application-specific PLLs or design custom PLLs in the following processes:

TSMC 0.25um G, 0.18um G and 0.13um G - online now

TSMC 90 Nanometer In development - target for full online release quarter two, 2003.

UMC 0.18um - online now

Silterra 0.18um via Silterra - online now 1st Silicon 0.25um FC via

1^st Silicon - online now