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Low Refresh Rate PLL for Video and Flat Panel Display Drivers

CEVA has developed a high performance PLL IP Core for use in Video and Flat Panel Display Applications that use the standard horizontal rate frequency to generate the required Pixel Rate Clock. Capable of accepting horizontal rate frequencies from 15 KHz to 110 KHz and providing pixel rates from 13 MHz to 230 MHz the CEVA Low Refresh PLL can accommodate many standard modes including VGA, SVGA, XGA, SXGA, UXGA, NTSC and a range of other modes. The core also includes a 16 step phase adjust mechanism used to deskew channels.

CEVA’s patented design controls phase drift maintaining typically <1ns input to output drift in most standard modes.

Proven in a number of processes including the TSMC 0.25um and a proprietary 0.13um IDM process the Low Refresh PLL has proved robust and portable across processes and geometry size.

 

  Typical Specification for Low Refresh PLL

 Parameter
Min
Typical
Max
 Input Clock (Horizontal Freq) KHz
15
 
110
 Output Clocks (Pixel Rate) MHz
13.5
 
229.5
 Period Jitter Sigma [pS]*
10
14
25
 Power [mW]
8
16
20
 Power Supply [V]
2
2.5
2.7
 Phase Drift (peak to peak) Input to output [nS]
1.6nS @30KHz Input
 Junction Temp [Deg]
0
-
125
 Lock Time (mS)
 
1.75
 
 Phase Adjust mechanism
16 Steps along output clock period

 

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Datasheet ( pdf 32kb)

How do I order this PLL?

Details on ordering this PLL from CEVA can be found here.

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