PLL for Set Top Box and MPEG applications targeted
at TSMC 0.13um G Process
CEVA’s 0.13um STB and MPEG
PLL is designed specifically to target the most common reference and clock
frequencies used in such applications. The PLL is delivered as a silicon
proven IP Core in GDSII format which can be easily integrated into all standard
CAD flows.
Operating Modes
refClk
(MHz)
Feedback
Divider
VCO Freq
(MHz)
Output
Divider
Clk o/p
(MHz)
13.5
16
216
16
13.5
13.5
16
216
8
27
13.5
16
216
4
54
Performance
Parameter
Typical Spec
VCO Jitter (1 sigma)
12ps
VCO Jitter (pk-pk)
140ps
Power Consumption
5mW
Area
0.24mm˛
Design Materials include
Verilog
Behavioral Model and Verilog Test Bench .lef
File for place and route .lib
file Datasheet
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Verilog
Behavioral Model and Verilog Test Bench
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