PLL for PCI - USB2.0 applications targeted at 0.18um
UMC
CEVA’s 0.18um PCI to USB2.0
PLL is designed specifically to target the most common reference and clock
frequencies used in such applications. The PLL is delivered as a silicon
proven IP Core in GDSII format which can be easily integrated into all standard
CAD flows.
Operating Modes
refClk
(MHz)
Input
Divider
PFD
Freq
Feedback
Divider
VCO Freq
(MHz)
33
11
3
160
480
66
22
3
160
480
Performance
Parameter
Typical Spec
VCO Jitter (1 sigma)
9ps
VCO Jitter (pk-pk)
94ps
Power Consumption
9mW @1.8V
Area
0.256mm˛
Design Materials include
Verilog
Behavioral Model and Verilog Test Bench .lef
File for place and route .lib
file Datasheet
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Verilog
Behavioral Model and Verilog Test Bench
121kb)
