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Spread Spectrum Clock Generator for EMI Sensitive Applications

CEVA has initiated the development of a high performance Spread Spectrum Clock Generator suitable for EMI sensitive applications. This IP core uses Spread Spectrum techniques to suppress electromagnetic interference from the PLL. This first device in a family of devices which are planned can accommodate Input clocks from 4 to 32MHz and generates Output Clocks from 16 to 128 MHz.

Initial designs are targeted at the TSMC and UMC 0.13um process but other processes can be considered on request.

 

  Target Spec for Spread Spectrum Clock Generator

 Parameter
Min
Typical
Max
 Input Clock Frequency MHz
4
  
32
 Output Clocks MHz
16
  
128
 Cycle to Cycle Jitter pS
 
90 @ 128MHz
150 @ 30MHz
250 @ 8MHz
350 @ 4MHz
 
 Lock Time us
 
300
 
 Power target mW
 
30
 
 Power down current uA
 
<20
 
 Area target
 
1mm*0.5mm
 
 Lock Time (mS)
  
1.75
  
 Junction Temp [Deg]
0
-
100
 Ambient Temp [Deg]
0
-
70

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Datasheet ( pdf 32kb)

How do I order this PLL?

Details on ordering this PLL from CEVA can be found here.

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