PLL up to 533MHz for DDR applications targeted at 0.18um
UMC
CEVA’s 0.18um DDR PLL is
designed specifically to target the most common reference and clock frequencies
used in DDR applications. The PLL is delivered as a silicon proven IP Core
in GDSII format which can be easily integrated into all standard CAD flows.
Operating Modes
Input
Freq
Input
Divider
PFD
Freq
F/B
Divider
VCO
Freq
Output
Clk
Output
Divider
Nominal O/P
Freq (MHz)
100
4
25.00
20
500
Clk 1
1
500
100
4
25.00
20
500
Clk 2
2
250
133.33
5
26.66
20
533.33
Clk 1
1
533.33
133.33
5
26.66
20
533.33
Clk 2
2
266.66
Performance
Parameter
Typical Spec
VCO Jitter (1 sigma)
6ps
VCO Jitter (pk-pk)
92ps
Power Consumption
15mW @ 1.8V
Area
0.249mm˛
Design Materials include
Verilog
Behavioral Model and Verilog Test Bench .lef
File for place and route .lib
file Datasheet
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Verilog
Behavioral Model and Verilog Test Bench
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