PLL for Digital Audio Applications targeted at 0.18um
UMC
CEVA’s 0.18um Digital Audio PLL is designed
specifically to target the most common reference and clock frequencies used
in such applications. The PLL is delivered as a silicon proven IP Core in
GDSII format which can be easily integrated into all standard CAD flows.
Operating Modes
refClk
(MHz)
Feedback
Divider
VCO Freq
(MHz)
Output
Divider
Clk o/p
(MHz)
4.5
49
220.5
5
44.1
4.5
64
288
6
48
4.5
64
288
9
32
Performance
Parameter
Typical Spec
VCO Jitter (1 sigma)
7.5ps
VCO Jitter (pk-pk)
100ps
Power Consumption
13mW @1.8V
Area
0.273mm˛
Design Materials include
Verilog
Behavioral Model and Verilog Test Bench .lef
File for place and route .lib
file Datasheet
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Verilog
Behavioral Model and Verilog Test Bench
118kb)
