PLL 33MHz to 266MHz for AGP applications targeted at
TSMC 0.13um G Process
CEVA’s 0.13um PLL for AGP
(Accelerated Graphics Port) applications is designed specifically to target
the most common reference and clock frequencies used in AGP applications.
The PLL is delivered as a silicon proven IP Core in GDSII format which can
be easily integrated into all standard CAD flows.
Operating Modes
Input
Freq
Input
Divider
PFD
Freq
F/B
Divider
VCO
Freq
Output
Clk
Output
Divider
Nominal O/P
Freq (MHz)
33.33
1
33.33
8
266.6
Clk 1
1
266.6
33.33
1
33.33
8
266.6
Clk 2
2
133.3
33.33
1
33.33
8
266.6
Clk 3
4
66.66
66.66
2
33.33
8
266.6
Clk 1
1
266.6
66.66
2
33.33
8
266.6
Clk 2
2
133.3
66.66
2
33.33
8
266.6
Clk 3
4
66.66
Performance
Parameter
Typical Spec
VCO Jitter (1 sigma)
12ps
VCO Jitter (pk-pk)
140ps
Power Consumption
5mW
Area
0.26mm˛
Design Materials include
Verilog
Behavioral Model and Verilog Test Bench .lef
File for place and route .lib
file Datasheet
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Verilog
Behavioral Model and Verilog Test Bench
109kb)
