This Programmable PLL generates
many of the most commonly used clock frequencies from just two simultaneous
outputs spanning frequencies from 300MHz to 1000MHz. Designed for flexibility
this wideband PLL is a good general purpose PLL capable of being used for
many different applications. The PLL is offered as an IP Core in GDSII format
on a Pre-Silicon basis pending evaluation of CEVA’s 90nm calibration
chip.
Operational Modes - 300MHz
to 1000 MHz Programmable PLL IP Core
Input
Freq
Input
Divider
PFD
Freq
F/B
Divider
VCO
Range
Output
Clk
Output
Divider
Min O/P
(MHz)
Nominal O/P
Freq (MHz)
Max O/P
(MHz)
15 to 1000 MHz
Program 1 to 50 in Integer steps
15 to 25 MHz
Program 30 to 50 in Integer steps
600 to 1000MHz in 20 MHz steps
Clk 1
1
600.0
800.0
1000.0
Clk 2
2
300.0
400.0
500.0
Performance
Parameter
Typical Spec
VCO Jitter (1 sigma)
8ps
VCO Jitter (pk-pk)
96ps
Power Consumption
5mW
Area
0.23mm˛
Design Materials include
Verilog
Behavioral Model and Verilog Test Bench .lef
File for place and route .lib
file Datasheet
Verilog
Behavioral Model and Verilog Test Bench
193kb)
