25 MHz to 600 MHz Multi-purpose Programmable PLL targeted
at 0.18um UMC
CEVA’s 0.18um Multi-purpose
Programmable PLL is designed specifically with flexibility in mind. With
seven simultaneous output clocks ranging in frequency from 25MHz to 600MHz
this is a good general purpose PLL capable of being used for many different
applications. The PLL is delivered as a silicon proven IP Core in GDSII
format which can be easily integrated into all standard CAD flows.
Operational Modes - General
Purpose Programmable PLL IP Core
Input
Freq
Input
Divider
PFD
Freq
F/B
Divider
VCO
Range
Output
Clk
Output
Divider
Min O/P
(MHz)
Nominal O/P
Freq (MHz)
Max O/P
(MHz)
5 to 150 MHz
Program 1 to 30 in Integer steps
3.75 to 6.25 MHz
Program 75 to 125 in Integer steps
375 to 625 MHz in 5 MHz steps
Clk 1
1
375.0
500.0
625.0
Clk 2
2
187.5
250
312.5
Clk 3
3
125.0
166.7
208.3
Clk 4
4
93.8
125.0
156.3
Clk 5
6
62.5
83.3
104.2
Clk 6
10
37.5
50.0
62.5
Clk 7
16
23.4
31.3
39.1
Performance
Parameter
Typical Spec
VCO Jitter (1 sigma)
6.3ps
VCO Jitter (pk-pk)
90ps
Power Consumption
23mW @ 1.8V
Area
0.308mm˛
Design Materials include
Verilog
Behavioral Model and Verilog Test Bench .lef
File for place and route .lib
file Datasheet
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Verilog
Behavioral Model and Verilog Test Bench
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