This Programmable PLL has two simultaneous
outputs capable of providing clocks from 110MHz to 375MHz. Designed for
flexibility this is a good general purpose PLL capable of being used for
many different applications. The PLL is offered as an IP Core in GDSII format
on a Pre-Silicon basis pending evaluation of CEVA’s 90nm calibration
chip.
Operational Modes - 110MHz
to 375 MHz Programmable PLL IP Core
Input
Freq
Input
Divider
PFD
Freq
F/B
Divider
VCO
Range
Output
Clk
Output
Divider
Min O/P
(MHz)
Nominal O/P
Freq (MHz)
Max O/P
(MHz)
2 to 400 MHz
Program 1 to 200 in Integer steps
1.5 to 2.5 MHz
Program 112 to 188 in Integer steps
266 to 374 MHz in 2 MHz steps
Clk 1
1
225.0
300.0
375.0
Clk 2
2
112.5
150
187.5
Performance
Parameter
Typical Spec
VCO Jitter (1 sigma)
11.5ps
VCO Jitter (pk-pk)
140ps
Power Consumption
5mW
Area
0.44mm˛
Design Materials include
Verilog
Behavioral Model and Verilog Test Bench .lef
File for place and route .lib
file Datasheet
Verilog
Behavioral Model and Verilog Test Bench
165kb)
155kb)
