CEVA offers a wide range of "Ready to Go" PLLs that are available
for immediate delivery. Offered on a number of foundrys and processes
these PLLs are all silicon proven in a CEVA calibration chip. Covering
a variety of specific and multi-purpose applications the one thing all
these PLLs have in common is that they are available NOW. Some of the
applications covered include:
DDR up
to 533MHz AGP to 266MHz
PCI - USB2.0
Set Top
Box and MPEG Digital
Audio A generic
Multi-purpose PLL A set of
90nm PLLs for select frequency ranges
Highlighting CEVA's commitment to advanced technologies CEVA
has designed a range of PLLs for the TSMC 90nm process which are also
available under our "Ready to Go" program. Our calibration chip including
a fully configurable PLL and 3 fixed PLLs was taped out in Dec 2002. Results
are expected in May 2003. Four PLLs covering a range of different frequencies
are offered on a pre-release basis to customers designing 90nm products
on the TSMC shuttle in 2003. Features include:-
Input
Clock :
Output
Clock :
Dividers:
5 to 300MHz
PLL1 = 50MHz to 1250MHz, multi-purpose
PLL2 = 110MHz to 375MHz for high frequency clock requirements
PLL3 = 187MHz to 625MHz for mid range frequency requirements
PLL4 = 300MHz to 1000MHz for lower frequency requirements
CEVA has designed a range of Application Specific PLLs to cover
some of the most common operational modes used in such applications as
AGP, DDR, PCI to USB, STB & MPEG and Digital Audio. These compiler generated
PLLs are also available under our Ready to Go program.
In addition CEVA has identified a number of applications
that require specific performance characteristics from the PLL.
For example-
Sonet
applications have ultra low jitter requirements Video
and Flat Panel Display applications have very tight input
to output Phase Drift requirements for Pixel Clock generation
EMI
Sensitive applications use Spread Spectrum techniques to achieve
EMI reduction
CEVA has developed a number of custom architectures to
address these specific characteristics.
"Low
Refresh Rate PLL" CEVA has developed a high performance PLL
IP Core for use in Video and Flat Panel Display applications that use
the standard horizontal rate frequency to generate the required Pixel
Rate Clock. Capable of accepting horizontal rate frequencies from 15
KHz to 110 KHz and providing pixel rates from 13 MHz to 230 MHz the
CEVA Low Refresh PLL can accommodate many standard modes including
VGA, SVGA, XGA, SXGA, UXGA, NTSC and a range of other modes. The core
also includes a 16 step phase adjust mechanism. CEVA's patented
design controls phase drift, maintaining typically <1.6ns input to output
drift in most standard modes.
"LC
Tank PLL" CEVA has developed an ultra-low jitter PLL IP Core
for use in Sonet applications. Running at a VCO Frequency of 2.488GHz
the CEVA "LC Tank PLL" has 1-sigma period jitter of <1ps.
"Spread
Spectrum PLL" CEVA has developed a Spread Spectrum Clock
Generator (or PLL) which is targeted at EMI sensitive applications.
CEVA's SSCG operates at clock frequencies from 20 to 150 MHz
and uses a patented technique to achieve the most efficient profile
for EMI reduction.
PLLXpert Online is a unique PLL Compiler, which allows you to
make
real-time decisions online about the PLL performance requirements
for your system. design
your own PLL online eliminating the waiting for vendor feedback get
all the deliverables you need to do top level design and integration
PLLXpert Online has been widely adopted by both digital and analog designers
who are excited about the flexibility that it provides in their project
planning and design decision-making. Processes available today include:-
TSMC 0.13um G TSMC 0.18um
UMC 0.18um
Silterra 0.18um 1st
Silicon 0.18um 1st
Silicon 0.25um FC
CEVA recognizes that not all requirements can be covered
by a set of application specific or compiler generated PLLs. We
specialize in offering those custom modifications that can sometimes
make your design more flexible and efficient. Whether they are
minor modifications or major design changes our skilled design
team has the experience and knowledge to interpret your requirements
and deliver the highest quality solutions. Examples of prior customizations
include:-
The addition of mux logic to allow PLL outputs to be selected
in specific sets
Non integer output dividers such as 1.5 and 2.5 ratios
The addition of range bits enabling multi-octave VCO capability
Bandwidth customization to compensate for excess input jitter
Multi-phase VCO outputs
"My PLLXpert Online" is a unique compiler concept whereby CEVA
will port it PLL Compiler to your foundry or IDM process. We provide
an account facility, which you can administer yourself, such that
your engineers and Customers can design and receive PLLs on your
process.
PLLXpert Online enables your engineers to make key design
decisions about their PLL and ASIC design requirements in real
time without waiting days for vendor feedback to PLL performance
inquiries.
Key features of My PLLXpert Online include:-
Dedicate account access to the PLLXpert Online compiler
Administration capability to manage your engineering and purchasing
users Optional
facility to enable your customers engineers to access your account and
generate PLLs on your process
Front end deliverables are generated and can be delivered automatically
to all users
(datasheets, Verilog behavioral models,
Lib and Lef files)
IP Core deliverables (CDL and GDSII) can be downloaded by designated
purchasing users
DDR up
to 533MHz 
