CEVA has designed a range of PLLs for the TSMC 90nm process. Capitalizing on the successful structures used in our 0.13um architecture, we are highly confident of first pass success with 90nm, our 6th Generation PLL. In total four PLLs are offered on a pre-release basis to customers targeting their first 90nm products at the TSMC shuttle program in 2003. Design materials and GDSII are available for immediate delivery.
Our calibration chip including a fully configurable PLL and 3 fixed PLLs was taped out in Dec 2002. Results are expected in May 2003.
Click the box corresponding to your frequency requirements in the table below to view and download your PLL design materials. Other frequency ranges available on request.
