July 03 2003 : eSilicon Announces Successful
Deployment of ASIC Chip Incorporating ParthusCeva PLL IP press
release | pdf
July 03 2003 : Chip Express Announces Successful
Deployment of Structured ASIC Products Incorporating ParthusCeva PLL IP
press release | pdf
April 15 2003 : ParthusCeva Announces Extensive Upgrade to PLLXpert
Online and the Addition of TSMC 0.13um PLL Compilers press
release | pdf
Webcast
TechOnLine Webcast
PLL IP for next generation ASIC or SoC design from 0.18um to 90nm.
Choosing the right PLL IP for your next generation ASIC or SoC
design could be the difference between first pass success and failure.
Being the only analog component in many all digital ICs the PLL
is often the most critical element in the design. In this presentation
ParthusCeva reviews PLL characteristics from the systems perspective,
analyze which PLL characteristics most affect system performance
and how these factors influence PLL design. more
information / view webcast
April 14, 2003 - San Francisco - ParthusCeva Inc. is adding models
of phase-locked loops for the 0.13-micron process of foundry Taiwan
Semiconductor Manufacturing Co. to PLLXpert, its Web site of PLL
design information and intellectual-property (IP) cores. full
article
